1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a fluidic assembly process for the placement of top-contact light emitting diodes on a transparent display substrate.
There are three major processes in the fabrication of gallium nitride (GaN) micro light emitting diode (μLED) disks for use in direct emission displays. These processes are: GaN μLED disk fabrication; GaN μLED disk distribution onto a transparent substrate; and, GaN μLED disk interconnection.
Since μLED disks distribute themselves randomly inside transparent substrate placement wells, it makes conventional IC style contact hole opening/metal interconnection design extremely challenging. Extra tolerances can be required in the (opaque) interconnections to address this random distribution, resulting in a substantial loss in the emission area fill factor. Further, the complexity required to make these connections can result in either a poor yield and/or high cost.
FIGS. 1A and 1B are plan views of a top-contact LED disk located in a substrate well. In FIG. 1A, Dd denotes the diameter of the LED (e.g., gallium nitride (GaN)) disk, Dr denotes the diameter of the micro-cavity or well into which the μLED disk has been distributed, and Dp denotes the diameter of the p-doped GaN (p-GaN) area, assuming the p-GaN is formed on the top of the disk. Area 100 is the n-GaN contact, where the p-GaN 102 and MQW have been removed by a reactive ion etch (RIE). The inner circular area 102 is the full LED stack with p-GaN on top. A layer of nickel oxide (NiOx)/indium tin oxide (ITO) may be formed on the surface of area 102. In considering typical photolithography misalignment tolerances (up to 2 microns (μm)), the circular area 102 is off the GaN disk center by 2 μm. Since only the area 102 can emit light, the emission area fill factor is only about 70.6%. Nearly 30% of emission area is lost due to the n-GaN opening 100.
FIG. 1B shows the working area for anode end connection 104 (Dpc). Connects made outside of the 24 μm diameter area 104 are likely to result in either a short circuit or open circuit. Conventional metal interconnection to the n-GaN area 102 further reduces the emission area fill factor. Only 31.4% area of the GaN disk will emit light in this example.
FIG. 2 is a partial cross-sectional view of a bottom cathode contact architecture. This option avoids the significant emission area fill factor loss associated with a conventional top-contact LED disk. A bottom interconnection electrode 200 is first evaporated and patterned on a substrate 202, followed by micro-cavity (well) 204 formation. A thin layer low melting temperature metal film 206 is then coated on the bottom electrode surface inside the micro-cavity 204. The GaN disk 208 (n-GaN 210/p-GaN 212) is then distributed into the micro-cavity 204. After the interlayer dielectric film 214 patterning, the top interconnection electrode 216 is evaporated and patterned to complete the whole process flow.
The process flow described by FIG. 2 is relatively simple. The front-side emission area fill factor can possible reach a maximum of 85% with a carefully top metal wiring design. Major challenges of this flow include the bottom contact yield, uniformity, reliability and repeatability, and the tradeoff between the bottom contact yield and the bottom electrode area if a backside emission opening is needed.